Semiconductor device and its manufacturing method

ABSTRACT

A method for manufacturing a semiconductor device wherein both the threshold voltages of an N-type MISFET and a P-type MISFET are low, device can be easily manufactured at a lower cost and a higher product yield, and the reliability of the gate insulation film is higher. The gate insulation film is formed on the surface of a silicon substrate  1  in N-type MISFET forming region and the P-type MISFET forming region, and metal gates  4  and  5  are provided thereon. The metal gate  4  is made from a TiCoN film, and the work function thereof is set at 4.0 to 4.8 eV suited to the gate electrode material of the N-type MISFET. The metal gate  5  is formed from a portion of the TiCoN film by ion-implantation of oxygen into the TiCoN film configuring the gate electrode  4  at a dosage of 1013 to 1014 (ions/cm2) to raise the work function by around 0.2 to 0.8 eV.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device and a method formanufacturing the same, and more particularly, to a semiconductordevice, which includes an N-channel metal-insulator-semiconductorfield-effect transistor (MISFET) and a p-channel MISFET both havingmetal gates and is capable of reducing a threshold voltage of each ofthe FETs to realize a higher operational speed.

BACKGROUND TECHNOLOGY

For increasing the integration density as well as improving theperformances of semiconductor devices, development of finer structureshas been achieved for the MISFETs constituting the semiconductor device.However, since the finer structure of the MISFET increases the influenceby the short-channel effect thereof, it is an important subject toreduce the short-channel effect. Among other proposals for thesuppression of the short-channel effect based on the technique inaccordance with a so-called scaling rule, a proposal uses a reducedthickness of the gate insulation film. This technique suppresses theshort-channel effect by reducing the thickness of the gate insulationfilm, in order to easily control the depletion layer formed in the Sisubstrate while applying a voltage to the gate insulation film.

However, if the gate electrode of the MISFET is made from polysilicondoped with impurities, there occurs a phenomenon that the depletionlayer is formed also in the gate electrode in the case where theelectric field applied to the gate electrode is relatively stronger dueto the thickness reduction of the gate insulation film. This results ina larger effective thickness of the gate insulation film.

For solving this depletion problem of the gate electrode, there is aproposal that the gate electrode should be made from a metallicmaterial. The metal gate made from the metallic material has theadvantages of reduction in the resistance of the gate electrode andsuppression of boron penetration, in addition to the advantage of abovesuppression of the gate electrode. Thus, the metal gate made of Al, W,WTi or nitride thereof was used in the initial stage of development ofthe MIS semiconductor devices.

However, there are following problems in the metal gate. For example,since Al has a melting point of as low as about 660 degrees C., a heattreatment at a temperature of equal to or above 400 degrees C., ifperformed for the purpose of activation of the source and drain, raisesthe problems of disconnection of the gate electrode and diffusion of theAl atoms into the peripheral area. In addition, there is a problem inthat W changes the characteristic thereof due to oxidation. Furthermore,there is problem in that W and WTi have lower resistances againstcleaning and are dissolved during an acid cleaning treatment.

Assuming that the gate electrode is made of a TiN film, for example,which is controlled in the alignment thereof, the work function of thegate electrode is improved in the reproducibility thereof. Thus, studyfor using the TiN as the gate electrode material has been conducted, asdescribed in Patent Publication JP-A-2001-15756, for example. However,since the work function of the TiN is around 4.6 eV, and thus resides inthe vicinity of midgap of silicon, i.e., in the intermediate valuebetween the Ec and the Ev of the silicon substrate, both the N-typeMISFET and P-type MISFET have higher threshold voltages (Vth). Morespecifically, a finer structure of the device employed in accordancewith the scaling rule, the power dissipation will increase. Although itis generally effective to reduce the power supply voltage for reductionof the power dissipation, the threshold voltage must be reducedaccordingly. If the metal gate is made of TiN, the threshold voltage(Vth) is excessively high for the MISFET of a sub-100-nm gate-lengthgeneration, as a result of which there arises the problem that thecurrent driveability thereof is decreased.

In view of the above, metal gate materials for the N-type MISFET andP-type MISFET are desired which are capable of suppressing thethresholds of the N-type MISFET and P-type MISFET. It is impossible tosignificantly change the work function of the metal by adjusting theimpurity concentration thereof, unlike the polysilicon. Thus, forchanging the threshold of the metal gate, it is necessary to employdifferent kinds of metals configuring the gate electrode. Examples ofthe proposed metallic materials having work functions around 4 eV suitedto the gate metal of the N-type MISFET (hereinafter referred to asN-type MIS metal) include Hf, Zr, Al, Ti, Ta and Mo. Examples of themetallic materials having work functions around 5 eV suited to theP-type MISFET (referred to as P-type MIS metal) include RuO₂, WN, Ni,Ir, Mo₂N, TaN and Pt. Table 1 tabulates the work functions of metalsrecited in literatures. The work functions shown in Table 1 are valuesrecited in literature “Applied Physics, vol. 69, No. 1 (2000), pp 4-14”,literature “Journal of Vacuum Science and Technology B16(2) pp. 829(1998) etc. Satisfactorily lower threshold voltages can be obtained forboth the N-type MISFET and P-type MISFET by a combination of one of theabove metallic materials selected as the gate electrode material for theN-type MISFET and one of the above metallic materials selected as thegate electrode material for the P-type MISFET.

TABLE 1 Metal Gate Material Work Function (eV) Hf 3.9 Zr 4.05 ZrN 4.7 Al4.08 Ti 4.17 Ta 4.19 Mo 4.2 W 4.52 TiN 4.7 Ru 4.71 RuO2 4.9 WN 5.0 Ni5.15 Ir 5.27 Mo2N 5.33 TaN 5.41 Pt 5.65

However, it is very difficult to manufacture a device including suchN-type MISFET and P-type MISFET by using a conventional technique formanufacturing the device. The reasons therefor will be describedhereinafter. For differentiating the gate electrodes of the N-typeMISFET and P-type MISFET in the fabrication, it is necessary to form anN-type MIS metallic film on the substrate, detach the N-type MISmetallic film in the area for forming therein the P-type MISFET and forma P-type MIS metallic film therein. However, since the metal forconfiguring the gate electrode must be chemically stable, the metal isdifficult to etch accordingly and is likely to damage the gate oxidefilm. In the submicron MISFETs, since the gate oxide film has athickness of 2 nm or less, it is very difficult to detach the N-type MISmetallic film without damaging the gate oxide film, and also difficultto reform a gate oxide film having an excellent property. In addition,since different kinds of metals configuring the gate electrodes needdifferent process conditions, there arise the problems of complexadjustments of the process conditions as well as impossibility ofemploying common process conditions. Further, these metals must satisfya variety of conditions such as excellent resistance against thecleaning accompanied by detachment of the gate metal, effectiveprevention of channeling during ion implantation after configuration ofthe gate electrodes, stability of interface between the gate electrodeand the gate oxide film during a heat treatment reaching up to atemperature of about 1000 degrees C. etc.

Another technique in accordance with the scaling rule is known whichforms dummy gate electrodes on the gate oxide film of the P-typeMISFETs, deposits a metallic film over an entire area for use as thegate electrodes of the N-type MISFETs, removes the dummy gate electrodesand deposits another metallic film on the gate oxide film of the P-typeMISFETs for use as the gate electrodes of the P-type MISFETs. Thistechnique also includes the step of removing the dummy gate electrodesformed on the gate insulation film, and damages the gate insulation filmin the process.

Thus, a technique using a damascene process is proposed for solving theproblems accompanied by the etching of the gate electrode and the heattreatment for activating the source and drain. Patent PublicationJP-A-2000-315789, for example, describes in the first embodiment thereofthe technique as detailed below. A HfO₂ film is formed as a gateinsulation film in the trenches of gate portions of the N-type MISFETand P-type MISFET formed as depressions, followed by forming a HfN film.Thereafter, the portion other than the gate electrodes of the P-typeMISFETs is protected by a resist, followed by selectively removing theHfN film on the gate electrode portions of the P-type MISFETs by using ahydrogen peroxide solution. Subsequently, a Co film is deposited in theentire area. This provides layered films including HfN film and Co filmfor the gate electrodes of the N-type MISFETs, whereas a single Co filmfor the gate electrodes of the P-type MISFETs. Thus, two kinds ofdifferent gate electrodes can be formed for the N-type MISFETs andP-type MISFETs. The HfN film has a small thickness of around 10 nm forthe purpose of preventing the etching from proceeding in the lateraldirection during the etching removal of the HfN film. JP-A-2000-315789recites that such a structure provides lower threshold voltages for boththe N-type MISFETs and P-type MISFETs.

However, since the threshold voltage of the MISFET is strongly affectedby the situation of the electrons in the interface between the gateinsulation film and the gate electrode, the threshold voltage of theMISFET varies widely to cause a lower product yield of the semiconductordevices unless the HfN film formed in the trenches is completelyremoved. The complete removal of the HfN film and the protection of thegate insulation film are tradeoffs and thus very difficult to becompatible. Furthermore, the two kinds of gate electrodes, if formed bythe damascene process, raises the problem of complicating the process toincrease the fabrication cost and reduce the product yield.

For solving the problems of detachment of the metallic film as describedbefore, another technique is proposed which uses ion-implantation ofnitrogen into a Mo film. For example, Qiang Lu et al. disclose atechnique for depositing a Mo film for use as the gate electrodes of theN-type MISFET and P-type MISFET, followed by controlling the workfunction of the P-type MISFET by ion-implantation of nitrogen into onlythe gate electrode of the P-type MISFET. Using this technique, theabsence of the step of detaching the gate electrode in contact with thegate insulation film solves the problem of complicated processaccompanied by the detachment of the metal and the wide range ofvariation of the threshold.

However, the above conventional technique involves the problems as shownhereinafter. In the technique of ion-implantation of nitrogen into theMo film, the pure metal, Mo, in direct contact with the silicon oxidefilm in the N-type MISFET raises the problem of degradation of thethermal stability of the interface. In addition, the ion-implantation ofnitrogen into the Mo film allows the nitrogen to be introduced also intothe silicon oxide film, or gate insulation film, thereby involving theproblem of degrading the long-term reliability of the gate insulationfilm.

DISCLOSURE OF THE INVENTION

In view of the above problems, the present invention is devised toprovide a semiconductor device having lower threshold voltages, capableof being manufactured at a low cost with a higher product yield andincluding a gate insulation film having a higher reliability, and amethod for manufacturing the same.

The present invention provides, in a first aspect thereof, asemiconductor device including a metal-insulator-semiconductorfield-effect transistor, characterized in that themetal-insulator-semiconductor field-effect transistor includes a gateelectrode made from a metallic, alloy or metal nitride film doped withoxygen or fluorine.

In accordance with the semiconductor device of the first aspect of thepresent invention, due to the gate electrode being made from a metallic,alloy or metal nitride film doped with oxygen or fluorine, the workfunction of the gate electrode can be arbitrarily controlled. Thisallows a metal gate having a lower threshold voltage to be formed withease. In addition, since ion-implantation of nitrogen into the gateelectrode is not needed upon forming this metal gate, the reliability ofthe gate insulation film is not damaged. The oxygen or fluorine,introduced into the gate electrode, does not damage the long-termreliability of the gate insulation film. It is to be noted that the“metal nitride” used in this text includes a nitride of a pure metal anda nitride of an alloy.

The present invention provides, in a second aspect thereof, asemiconductor device including an N-channelmetal-insulator-semiconductor field-effect transistor and a P-channelmetal-insulator-semiconductor field-effect transistor, characterized inthat the N-channel metal-insulator-semiconductor field-effect transistorincludes a gate electrode made from a metallic, alloy or metal nitridefilm doped with oxygen or fluorine, and that the P-channelmetal-insulator-semiconductor field-effect transistor includes a gateelectrode formed in a common layer with the gate electrode of theN-channel metal-insulator-semiconductor field-effect transistor and madefrom a portion of the common layer doped with oxygen or fluorine moreheavily than the gate electrode of the N-channelmetal-insulator-semiconductor field-effect transistor.

The present invention provides, in a third aspect thereof, asemiconductor device including an N-channelmetal-insulator-semiconductor field-effect transistor and a P-channelmetal-insulator-semiconductor field-effect transistor, characterized inthat the N-channel metal-insulator-semiconductor field-effect transistorincludes a gate electrode made from a metallic, alloy or metal nitridefilm, and that the P-channel metal-insulator-semiconductor field-effecttransistor includes a gate electrode formed in a common layer with thegate electrode of the N-channel metal-insulator-semiconductorfield-effect transistor and made from a portion of the common layerdoped with oxygen or fluorine.

In accordance with the semiconductor devices of the second and thirdaspects of the present invention, the gate electrode of the N-channelmetal-insulator-semiconductor field-effect transistor (hereinafter,referred to as N-type MISFET) is made from a material, which is a metal,an alloy or a nitride of a metal (hereinafter referred to collectivelyas metallic material), and the gate electrode of the P-channelinsulated-gage field-effect transistor (hereinafter referred as P-typeMISFET) is made from the common layer with the gate electrode of theN-type MISFET, the common layer being doped with oxygen or fluorine.More specifically, the gate materials of the N-type MISFET and theP-type MISFET are differentiated from each other in fabrication thereofby adding oxygen or fluorine into the material which is metal, alloy ornitride of a metal. This allows metal gates having work functions suitedto the N-type MISFET and P-type MISFET to be fabricated withoutdifficulty. As a result, the threshold voltages of the N-type MISFET andP-type MISFET can be reduced without involving depletion of the gateelectrodes. In addition, since ion-implantation of nitrogen into thegate electrodes is not needed upon forming the gate electrodes, thereliability of the gate insulation film is not damaged.

It is preferable that the material for forming the gate electrode of theN-type MISFET and the gate electrode of the P-type MISFET bepolycrystalline or amorphous and have an average grain size of not morethan 50 nm.

In general, the work function of a metal differs depending on the planeorientation. Accordingly, if the plane orientation of the materialconfiguring the gate electrodes differs between the gate electrodes, thethreshold of each transistor varies significantly to degrade theperformance of the semiconductor device. Since the gate length is equalto or less than 100 nm in these days, the variation of the threshold canbe prevented so long as the material configuring the gate electrodes ispolycrystalline or amorphous and has an average grain size of not morethan 50 nm, whereby the resultant transistors can be improved for theirperformances. It is to be noted that if it is possible to align theplane orientation of the material between the gate electrodes, thematerial need not be a polycrystalline or amorphous and need not have anaverage grain size of not more than 50 nm, and thus may be singlecrystalline, for example.

It is also preferable that the material configuring the gate electrodeof the N-channel metal-insulator-semiconductor field-effect transistorand the gate electrode of the P-channel metal-insulator-semiconductorfield-effect transistor be made of an alloy including two or more metalsselected from the group consisting of Al, Si, Ti, V, Co, Ni, Ge, Zr, Nb,Mo, Ru, Hf, Ta and W or a nitride of the alloy. In this configuration,by adjusting the content ratio of the alloy, the work function of thealloy can be controlled in a wide range. As a result, the threshold ofthe transistor can be controlled in a wider range.

It is also preferable that the oxygen or fluorine profile of the gateelectrode of the P-channel metal-insulator-semiconductor field-effecttransistor with respect to a thickness direction thereof have a peakwithin 5 nm from the interface with the gate insulation film. In thisconfiguration, the influence applied on the work function of the gateelectrode of the P-type metal-insulator-semiconductor field-effecttransistor by the introduced oxygen can be increased, while reducing theinfluence on the resistance of this gate electrode. In addition, theresultant introduction of the oxygen into the gate insulation filmprevents reduction of the reliability of the gate electrode.

The present invention also provides, in a fourth aspect thereof, asemiconductor device including an N-channelmetal-insulator-semiconductor field-effect transistor and a P-channelmetal-insulator-semiconductor field-effect transistor, characterized inthat each of the N-channel metal-insulator-semiconductor field-effecttransistor the P-channel metal-insulator-semiconductor field-effecttransistor includes a gate insulation film and a gate electrode formedon the gate insulation film, that one of the gate electrodes includes afirst film formed on the gate insulation film and made of a firstmaterial which is either a metal, an alloy or a nitride of a metal, anda second film formed on the first film and made of a second materialwhich is either a metal, an alloy or a nitride of a metal, and that theother of the gate electrodes includes a third film formed on the gateinsulation film and made of the first material having a larger thicknessthan the first film.

In accordance with the semiconductor device of the fourth aspect of thepresent invention, the one of the gate electrodes includes the first andsecond films, whereas the other of the gate electrodes includes thethird film. This results in that the work function of the one of thegate electrodes is affected by the second film to be differentiated fromthe work function of the other of the gate electrodes. Accordingly,metal gates having work functions suited to the N-type MISFET and theP-type MISFET can be fabricated without difficulty. In addition, sinceion-implantation of nitrogen into the gate electrode is not needed, thereliability of the gate insulation film is not damaged.

It is preferable that the first film have an average thickness of notmore than 5 nm, and the third film have an average thickness of morethan 5 nm. In this configuration, the work function of the one of thegate electrodes is strongly affected by the second film, whereas thework function of the other of the gate electrodes can be stronglyaffected by the third film. It is to be noted that the average thicknessof the first film is obtained by measuring the concentration profile ofthe first film, and calculating the thickness thereof based on theconcentration profile while assuming that the first film is made of onlythe first material.

The present invention also provides, in a fifth aspect thereof, asemiconductor device including an N-channelmetal-insulator-semiconductor field-effect transistor and a P-channelmetal-insulator-semiconductor field-effect transistor, characterized inthat each of the N-channel metal-insulator-semiconductor field-effecttransistor and the P-channel metal-insulator-semiconductor field-effecttransistor includes a gate insulation film and a gate electrode formedon the gate insulation film, that one of the gate electrodes includes afirst film formed on the gate insulation film and made of a firstmaterial which is either a metal, an alloy or a nitride of a metal, anda second film formed on the first film and made of a second materialwhich is either a metal, an alloy or a nitride of a metal, and that theother of the gate electrodes includes the first film and a third filmformed on the first film and made of a third material which is either ametal, an alloy or a nitride of a metal.

The present invention also provides, in a sixth aspect thereof, a methodfor manufacturing a semiconductor device including ametal-insulator-semiconductor field-effect transistor, including thesteps of forming a gate insulation film on a semiconductor substrate inan area for forming the metal-insulator-semiconductor field-effecttransistor, forming a film made of a metal, an alloy or a metal nitrideon the gate insulation film, selectively introducing oxygen or fluorineinto the film, selectively removing the film to configure a gateelectrode pattern, and implanting impurities into a surface area of thesemiconductor substrate by using the gate electrode as a mask to therebyform source and drain.

The present invention also provides, in a seventh aspect thereof, amethod for manufacturing a semiconductor device including an N-channelmetal-insulator-semiconductor field-effect transistor and a P-channelmetal-insulator-semiconductor field-effect transistor, including thesteps of forming a gate insulation film on a semiconductor substrate inboth the areas for forming the N-channel metal-insulator-semiconductorfield-effect transistor and the P-channel metal-insulator-semiconductorfield-effect transistor, forming a film made of a metal, an alloy or ametal nitride on the gate insulation film, selectively introducingoxygen or fluorine into the film in the area for forming the P-channelmetal-insulator-semiconductor field-effect transistor, selectivelyremoving the film to configure a gate electrode, and selectivelyimplanting impurities into a surface area of the semiconductor substrateby using the gate electrode of the N-channelmetal-insulator-semiconductor field-effect transistor and the gateelectrode of the P-channel insulated-gage field-effect transistor as amask to thereby form sources and drains.

In accordance with the semiconductor device manufacturing methods of thesixth and seventh aspects of the present invention, since two kinds ofgate materials are formed while being differentiated from each other byimplanting oxygen or fluorine, the gate electrodes are fabricated moreeasily at a smaller cost and with a higher product yield compared to thecase where the two kinds of gate materials are separately formed bydifferent processes. In addition, since there is no step of removing theonce-deposited metallic film by etching etc., the gate insulation filmis not damaged. Further, due to the no damage of the gate insulationfilm caused by etching and no ion-implantation of nitrogen, the gateinsulation film has a higher reliability.

The present invention also provides, in an eighth aspect thereof, amethod for manufacturing a semiconductor device including an N-channelmetal-insulator-semiconductor field-effect transistor and a P-channelmetal-insulator-semiconductor field-effect transistor, including thesteps of forming dummy gate electrodes on a semiconductor substrate inboth areas for forming the N-channel metal-insulator-semiconductorfield-effect transistor and the P-channel metal-insulator-semiconductorfield-effect transistor, introducing impurities into a surface area ofthe semiconductor substrate by using the dummy gate electrodes as a maskto thereby form sources and drains, heat treating for activation of theimpurities, forming an interlayer dielectric film so as to embedperipheries of dummy gate electrodes, removing the dummy gate electrodesto thereby form grooves in the interlayer dielectric film, forming agate insulation film at least in the grooves, forming a film made of ametal, an alloy or a nitride of a metal on the gate insulation film,selectively introducing oxygen or fluorine in the film in the area forforming the P-channel metal-insulator-semiconductor field-effecttransistor, and selectively removing the film to thereby configure gateelectrodes.

In accordance with the semiconductor device manufacturing method of theeighth aspect of the present invention, dummy gate electrodes areformed, and impurities are implanted and activated, followed by removingthe dummy gate electrodes and forming the gate insulation film and gateelectrodes. In this configuration, the gate insulation film and gateelectrodes are not exposed to a heat treatment, whereby a gate electrodematerial having a relatively lower heat resistance in the interfacebetween the gate electrode and the gate insulation film can be used.

The present invention also provides, in a ninth aspect thereof, a methodfor manufacturing a semiconductor device including an N-channelmetal-insulator-semiconductor field-effect transistor and a P-channelmetal-insulator-semiconductor field-effect transistor, including thesteps of forming a gate insulation film on a semiconductor substrate inboth areas for forming the N-channel metal-insulator-semiconductorfield-effect transistor and the P-channel metal-insulator-semiconductorfield-effect transistor, forming on the gate insulation film a firstfilm made of a first material which is a metal, an alloy or a nitride ofa metal, forming on the first film a second film made of a secondmaterial which is a metal, an alloy or a nitride of a metal, selectivelyremoving the second film in one of the areas for forming the N-channelmetal-insulator-semiconductor field-effect transistor and the P-channelmetal-insulator-semiconductor field-effect transistor, forming a thirdfilm made of the first material in the one of the areas, selectivelyremoving the first through third films to configure gate electrodes ofthe N-channel metal-insulator-semiconductor field-effect transistor andthe P-channel metal-insulator-semiconductor field-effect transistor, andintroducing impurities into a surface area of the semiconductorsubstrate by using the dummy gate electrodes of the N-channelmetal-insulator-semiconductor field-effect transistor and the P-channelmetal-insulator-semiconductor field-effect transistor as a mask tothereby form sources and drains.

In accordance with the semiconductor device of the ninth aspect of thepresent invention, two kinds of gate electrodes of the N-type MISFET andthe P-type MISFET are formed by layering films made of metal, alloy ornitride of metal. This allows the work functions of the gate electrodesto be controlled at respective optimum values by selecting the kinds andthe thicknesses of the layered films. In addition, the work functions ofthe gate electrodes are controlled to differentiate the gate electrodeof the N-type MISFET and the gate electrode of the P-type MISFET in thefabrication without damaging the gate insulation film. As a result, asemiconductor device including an N-type MISFET and a P-type MISFEThaving lower threshold voltages can be obtained without involvingdepletion of the gate electrodes. Further, due to absence of the damageof the gate insulation film caused by etching, the reliability of thegate insulation film is not degraded. Further, the feasibility thereofreduces the fabrication cost and raises the product yield.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graph showing variation of the work functions of TiCo andTiCoN when the ratio between the numbers of atoms of Ti and Co ischanged, wherein the ratio between the numbers of atoms (Ti/(Ti+Co)) isplotted on abscissa and the work functions are plotted on ordinate.

FIG. 2 is a graph showing variation of the work function of TiWN whenthe ratio between the numbers of atoms of T1 and W is changed, whereinthe ratio between the numbers of atoms (W/(Ti+W)) is plotted on abscissaand the work function is plotted on ordinate.

FIG. 3 is a graph showing variation of the work function of HfZrN whenthe ratio between the numbers of atoms of HfN and ZrN is changed,wherein the ratio between the number of atoms (HfN/(HfN+ZrN)) is plottedon abscissa and the work function is plotted on ordinate.

FIG. 4 is a graph showing influence caused on the work function of TiNby a variety of additive metals, wherein the amount of implanted oxygenis plotted on abscissa and the work function of TiCoN is plotted onordinate.

FIG. 5 is a graph showing variation of the work function when oxygen isintroduced into TiCoN, wherein the amount of implanted oxygen is plottedon abscissa and the work function TiCoN is plotted on ordinate.

FIG. 6 is a sectional view of a semiconductor device according to afirst embodiment of the present invention.

FIGS. 7( a) to (d) are sectional views showing the semiconductor deviceof the first embodiment in the order of fabrication steps thereof.

FIGS. 8( a) to (d) and FIGS. 9( a) to (c) are sectional views showing asemiconductor device according to a second embodiment of the presentinvention in the order of fabrication steps thereof.

FIG. 10( a) is a side view showing the test method for investigating therelationship between the work function of layered films and thicknessratio, and FIG. 10( b) is a graph showing the influence caused by theaverage thickness of the TiN film on the work function of the layeredfilms, wherein the average thickness of the TiN film shown in FIG. 10(a) is plotted on the abscissa and the work function of the layered filmsshown in FIG. 10( a) is plotted on ordinate.

FIG. 11 is a sectional view of a semiconductor device according to athird embodiment of the present invention.

BEST MODES FOR CARRYING OUT THE INVENTION

The present inventors intensively studied for solving the above problemsand found that forming the gate electrodes from an alloy having aspecific composition allows the work function of this alloy to beeffectively controlled, and that ion-implanting oxygen or fluorine intothis alloy allows the work function of this alloy to be effectivelychanged. This results in that the gate electrode of an N-type MISFET andthe gate electrode of a P-type MISFET are differentiated from oneanother in the fabrication thereof.

Referring to FIG. 1, wherein the ratio between the numbers of atoms(Ti/(Ti+Co)) is plotted on abscissa and the work functions are plottedon ordinate, it is shown that work functions of TiCo and TiCoN vary whenthe ratio between the numbers of atoms of Ti and Co is changed.Referring to FIG. 2, wherein the ratio between the number of atoms(W/(Ti+W)) is plotted on abscissa and the work function is plotted onordinate, it is shown that the work function of TiWN varies when theratio between the number of atoms of Ti and W is changed. Referring toFIG. 3, wherein the ratio between the numbers of atoms (HfN/(HfN+ZrN))is plotted on abscissa and the work function is plotted on ordinate, itis shown that work function of HfZrN varies when the ratio between thenumbers of atoms of HfN and ZrN is changed. Referring to FIG. 4, whereinthe work functions of additive metals are shown on the abscissa and thework functions of the TiN alloys obtained by adding additive metals intoTiN at 10 atomic percents are plotted on ordinate, the influences causedby the additive metals on the work function are shown.

It is to be noted that the values of the work functions shown in FIGS. 1to 4 were measured in experiments by the present inventors. Some ofthese values are different to some extent from those recited in theliteratures shown in Table 1. This is because the measurement of thework functions is difficult to achieve, and the work function of thesame material may differ by about 0.5 eV depending on the planeorientation thereof. In addition, it is likely that some of theliteratures recite different work functions. In the present invention,the relative change of the work function is more important than theabsolute value of the work function itself, the relative change of thework function depending on the composition of the material of the gateelectrode, the oxygen or fluorine concentration thereof and thethickness of the gate electrode. Thus, for the purpose of convenience,the experimental values obtained by the present inventors are used asthe work functions in the description to follow.

As shown in FIG. 1, the work function of TiCo changes almost continuallyfrom 4.0 eV for Ti to 5.0 eV for Co along with the increase of the Cocontent. On the other hand, the work function of TiCoN exhibits a changedifferent from that of the work function of the TiCO, does notnecessarily assume an intermediate value between the work functions ofTiN and CoN, i.e., within 4.75 eV and 4.82 eV, and changes within therange between 4.4 eV and 5.5 eV. By taking advantage of thischaracteristic, a desired work function can be obtained within the rangebetween 4.4 eV and 5.2 eV while controlling the ratio between Ti and Coin the TiCoN. In addition, it was confirmed that the work function ofTiCo added with nitrogen exhibited a continual increase along with theincrease of the amount of nitrogen. More specifically, the work functionof TiCoN can be adjusted to a work function suited to the N-type MISFETand P-type MISFET by controlling the content ratio between Ti and Coand/or the content of N, with a broader design choice.

As shown in FIG. 2, the work function of the TiWN alloy deviates fromthe range between the work function of the TiN alloy and the workfunction of the WN alloy, i.e., from the range between 4.74 eV and 4.82eV, wherein the work function varies complicatedly with the change ofcontent of the TiWN alloy. In addition, it is recited in “Journal ofvacuum Science and Technology B16(2), pp 829 (1998)” that the workfunction of ZrN assumes about 4.7 eV (refer to Table 1). Accordingly, asshown in Table 1 and FIG. 3, the work function of the HfZrN alloydeviates from the range between the work function of the HfN alloy andthe work function of the ZrN alloy, varying complicatedly with thechange of the composition of the HfZrN alloy. Such a behavior is similarto the behavior of the TiCoN alloy shown in FIG. 1. In addition, asshown in FIG. 4, there is no clear correlation between the workfunctions of the additive metals added into TiN and the work functionsof the TiN alloys after the addition.

As described above, the present inventors found that the work functionof an alloy may sometimes deviate from the range between the workfunctions of the components constituting the alloy, and that the workfunction of this alloy changes complicatedly. It was found accordinglythat the work function of the alloy can be controlled as desired byselecting the optimum composition of the alloy after investigating therelationship between the composition of the alloy and the work functionthereof. It is to be noted that it is difficult to estimate the workfunction of the alloy from the work functions of the components of thealloy, and that, even if the work function of an alloy having a specificcomposition is found, it is difficult to estimate the work function ofanother alloy having the same components as the alloy and differentcomposition from that of the alloy. Thus, it is necessary toexperimentally obtain the relationship between the composition of thealloy and the work function thereof, as obtained by the presentinventors.

Referring to FIG. 5, wherein the amount of implanted oxygen ions isplotted on abscissa and the work function of TiCoN is plotted onordinate, the change of the work function when oxygen is ion-implantedinto the TiCoN is shown. As understood from FIG. 5, when oxygen ision-implanted into TiCoN, the work function increases with the increaseof the amount of ion-implantation and the behavior of increase issubstantially linear.

In a preferred embodiment of the present invention, characteristicsshown in FIGS. 1 and 5 are utilized. First, after selecting the speciesand composition of the alloy, a film made of the metallic materialhaving a work function suited to the gate electrode of the N-type MISFETis deposited in both the areas for forming the N-type MISFET and P-typeMISFET. Subsequently, oxygen is ion-implanted into the metallic film inthe portion thereof corresponding to the gate electrode of the P-typeMISFET, to change the work function of the film in the portioncorresponding to the gate electrode of the P-type MISFET into anotherwork function suited to the gate electrode of the P-type MISFET. Thespecies of ions implanted for controlling the work function is notlimited to oxygen, and may be fluorine or nitrogen to achieve a similareffect. However, if nitrogen is ion-implanted, the nitrogen ions arereceived in the gate insulation film, thereby degrading the reliabilityof the gate insulation film. Oxygen or fluorine does not degrade thegate insulation film, even if these elements are received in the gateinsulation film. Thus, the species of implanted ions must be oxygen orfluorine.

As described in the background technology, a technique forion-implanting nitrogen into the metal gate such as made of Ti or Mo isreported. However, in this technique, for significantly changing thework function of the metal gate, a larger amount of nitrogen must beimplanted. A larger amount of nitrogen, if implanted in the gateinsulation film, degrades the reliability of the gate insulation film.On the other hand, as shown in Table 2, the electronegativities ofoxygen and fluorine are larger than the electronegativities of metallicelements and nitrogen, thereby providing larger electron affinities.Accordingly, ion-implantation of oxygen or fluorine into the gateelectrode material even in a small amount can significantly increase thework function of the material. In addition, since the fluorine is anelement that may be used for improving a silicon oxide film, forexample, and the oxygen is one of the elements that configure the gateinsulation film, the reliability of the gate insulation film is notdegraded by implanting a small amount of these elements into the gateinsulation film. The ion-implantation of oxygen may be considered toincrease the resistance due to oxidation of the metal. However, sincethe amount of oxygen implanted is very small, and the oxygen islocalized in the interface between the gate oxide film and the gateelectrode, the electric resistance of the gate electrode is scarcelychanged.

TABLE 2 Element Ti Co W N O F Electronegativity 1.5 1.8 1.7 3.0 3.5 4.0

The present inventors found that the work function of an alloy includingtwo or more kinds of metals selected from the group consisting of Al,Si, Ti, V, Co, Ni, Ge, Zr, Nb, Mo, Ru, Hf, Ta and W, as well as anitride thereof, in addition to the above-described TiCoN, TiWN andHfZrN, also largely changes to deviate from the range between the workfunctions of the metals constituting the alloy. In addition, althoughthere are problems of lower resistances against heat and cleaning if Aland W are used in the gate electrode as pure metals, alloying thereofsolves these problems.

Hereinafter, embodiments of the present invention will be described moreconcretely with reference to accompanying drawings. For a start, a firstembodiment of the present invention will be described. FIG. 6 shows asemiconductor device according to the present embodiment. As shown inFIG. 6, in the semiconductor device of the present embodiment, a siliconsubstrate 1 is provided, and element isolation regions 2 are selectivelyformed in the surface area of the silicon substrate 1. An insulationfilm, such as made of SiO₂, is received in the element isolation region2, and the space between the element isolation regions 2 constitutes anN-type MISFET forming region 11 or a P-type MISFET forming region 12.The depth of the element isolation region 2 is 100 to 500 nm, forexample, whereas the distance between the element isolation regions is0.05 to 10 μm, for example.

In each of the N-type MISFET forming region 11 and P-type MISFET formingregion 12 in the surface area of the silicon substrate 1, two diffusedregions 8 are formed. The diffused region 8 is formed by implantation ofimpurity ions into the silicon substrate 1, adjacent to the elementisolation region 2. The width of diffused region 8 is 0.1 to 10 μm, forexample, and may be 0.2 μm, for example, the depth thereof is 50 to 500nm, for example, and may be 100 nm, and the impurity concentrationthereof is 10¹⁹ to 10²¹ cm⁻³, for example. In addition, an extensionregion 6 is formed adjacent to the diffused region 8 so as to sandwichthe diffused region 8 together with the element isolation region 2. Theextension region 6 is also formed by ion-implantation of impurities intothe silicon substrate 1, and the impurity concentration thereof isequivalent to or lower than that of the diffused region 8. The width ofthe extension region 6 is 60 nm, for example, the depth thereof is 5 to200 nm, for example, and the impurity concentration thereof is 10¹⁹ to10²¹ cm⁻³, for example.

On the silicon substrate 1, a gate insulation film 3 made from a siliconoxynitride film and having a thickness of 1 to 3 nm is formed. Metallicgate electrodes 4 and 5 are formed in the N-type MISFET forming region11 and P-type MISFET forming region 12, respectively, on the gateinsulation film 3. The thickness of the metal gates 4 and 5 is 20 to 200nm, for example, and may be 50 to 100 nm, for example. The metal gate 4is made of TiCoN having a composition ratio of Co:N=0 to 35:0 to 20, forexample, in atomic percent and a work function of 4.0 to 4.8 eV, whichis suited to the gate electrode material of the N-type MISFET. The metalgage 5 is made from a material wherein the TiCoN configuring the metalgate 4 is doped with oxygen by ion-implantation at a dosage of about10¹³ to 10¹⁴ (ions/cm³). The material configuring the metal gate 5 has awork function 0.2 to 0.8 eV higher than the work function of thematerial configuring the gate electrode 4, and may be 4.9 eV, forexample, which is suited to the gate electrode material of the P-typeMISFET. It is to be noted that the concentration profile of the oxygenin the thickness direction of the metal gate 5 has a peak within 5 nmfrom the interface with the gate insulation film 3. More specifically,the oxygen in the metal gate 5 is localized in the interface with thegate insulation film 3.

Moreover, around the metal gates 4 and 5, respective side-walls 7 areformed. The side-wall 7 is made from a silicon nitride film, forexample. Further, an interlayer dielectric film 9 made of a SiO₂, BPSG,SiN or low-dielectric-constant film is formed so as to embed theperipheries of the metal gates 4 and 5 and side-walls 7. The topsurfaces of the metal gates 4 and 5 are exposed from the top surface ofthe interlayer dielectric film 9.

In the above configuration, the silicon substrate 1, pair of diffusedregions 8, pair of extension regions 6, gate insulation film 3, metalgate 4 and side-wall 7 constitute the N-type MISFET in the N-type MISFETforming region 11. The diffused regions 8 constitute source and drain,and the gap therebetween constitutes a channel region. Similarly, thesilicon substrate 1, pair of diffused regions 8, pair of extensionregions 6, gate insulation film 3, metal gate 5 and side-wall 7constitute the P-type MISFET in the P-type MISFET forming region 12.

When a voltage is applied to the metal gate 4 in the N-type MISFETforming region, the channel region is applied with an electric field viathe gate insulation film 3, whereby the carrier concentration in thechannel region is changed. This results in a change of the currentflowing between the source and drain. Similarly, when a voltage isapplied to the metal gate 5 in the P-type MISFET forming region, thecurrent flowing between the source and drain is changed.

Next, a method for manufacturing the semiconductor device according tothe first embodiment will be described. FIGS. 7( a) to 7(d) show thesemiconductor device manufacturing method of the present embodiment inthe order of fabrication steps. As shown in FIG. 7( a), an insulationfilm is selectively embedded in the surface area of the siliconsubstrate 1, thereby forming therein element isolation regions 2. Theelement isolation region 2 is formed using a LOCOS technique(local-oxidation-of-silicon technique) or an STI technique (shallowtrench isolation technique), for example.

Subsequently, as shown in FIG. 7( b), a gate insulation film 3 isdeposited on the silicon substrate 1 to a thickness of 1 to 3 nm. Inthis step, after a ten-minute treatment, wherein the depositiontemperature, oxygen flow rate, nitrogen flow rate and deposition gaspressure are set at 750 degrees C., 0.05 milliliters/minute, 0.25milliliters/minute and 6.7 Pa, is performed to deposit a siliconoxynitride film having a nitrogen concentration of 10 atomic percentsand a thickness of 2 nm. Thereafter, a TiCoN film 4 a is deposited onthe gate insulation film 3 by using a sputtering technique or a CVD(chemical vapor deposition) technique. The TiCoN film has a contentratio of Co:N=0 to 35:0 to 20 in atomic percent, and a thickness ofabout 20 to 200 nm. The TiCoN film has a work function of 4.0 to 4.8 eV,which is suited to the gate electrode material of the N-type MISFET.Subsequently, the TiCoN film 4 a is patterned to configure a specificgate electrode pattern. Thus, the TiCoN film 4 a patterned in the N-typeMISFET forming region 11 configures the metal gate 4.

Subsequently, as shown in FIG. 7( c), a resist film (not shown) isformed so as to expose therefrom the patterned TiCoN film 4 a in theP-type MISFET forming region 12 and to cover the other regions.Thereafter, oxygen is selectively ion-implanted in the patterned TiCoNfilm 4 a in the P-type MISFET forming region 12 at an accelerationvoltage of 10 keV and a dosage of around 10¹³ to 10¹⁴ cm⁻². This resultsin an increase of the work function of the TiCoN film 4 a by about 0.2to 0.8 eV. Thus, the TiCoN film 4 a patterned in the P-type MISFETforming region 12 is configured to the gate electrode 5.

Subsequently, As ions are implanted in a self-aligned process in theN-type MISFET forming region 11 by using the metal gate 4 as a mask. Inthis step, the dosage of ion implantation is 1×10¹⁴ to 1×10¹⁵ cm⁻², forexample, and may be 5×10¹⁴ cm⁻², for example, whereas the accelerationvoltage is 2 kV, for example. Thereafter, by performing a heattreatment, the extension regions 6 in the N-type MISFET forming region11 are formed. In this step, the temperature of the heat treatment is900 to 1100 degrees C., for example, and the time length thereof isabout 20 seconds or less, for example.

Subsequently, BF₂ ions are implanted in a self-aligned process into theP-type MISFET forming region 12 by using the gate electrode 5 as a mask.In this step, the dosage of ion-implantation is 1×10¹⁴ to 1×10¹⁵ cm⁻²,for example, and may be 5×10¹⁴ cm⁻², for example, and the accelerationvoltage is 2.5 kV, for example.

Subsequently, as shown in FIG. 7( d), a silicon nitride film isdeposited on the peripheries of the gate electrodes 4 and 5, followed byetch-back thereof to form side-walls 7 on the metal gates 4 and 5.Thereafter, As or P ions are implanted in a self-aligned process intothe N-type MISFET forming region 11. The dosage of ion-implantation is5×10¹⁴ to 2×10¹⁶ cm⁻², for example, and if As ions are implanted, thedosage of ion-implantation is 4×10¹⁵ and the acceleration voltagethereof is 8 kV, whereas if P ions are implanted, the dosage ofion-implantation is 1×10¹⁵ cm⁻², and the acceleration voltage is 10 kV.Subsequently, B ions are implanted in a self-aligned process in theP-type MISFET forming region. In this step, the dosage ofion-implantation is 5×10¹⁴ to 2×10¹⁶ cm⁻², for example, and may be3×10¹⁵ cm⁻², whereas the acceleration voltage is 2 keV. Thereafter, arapid thermal annealing (RTA) is performed for impurity activation,thereby forming deep diffused regions 8, which constitute source anddrain regions, as well as extension regions 6 in the P-type MISFETforming region 12. The temperature of the rapid thermal annealing is 900to 1100 degrees C., for example, and the time length of the rapidthermal annealing is 20 seconds or less, for example.

Thereafter, as shown in FIG. 6, an interlayer dielectric film 9 made ofa SiO₂, BPSG, AiN or low-dielectric-constant film is deposited on thegate insulation film 3 so as to embed the peripheries of the gateelectrodes 4 and 5 and the side-walls 7. Thus, the semiconductor deviceaccording to the present embodiment is obtained.

It is to be noted that, if the TiCoN film configuring the metal gates 4and 5 has a thickness of 5 nm or larger, the work function of the metalgates 4 and 5 do not change upon deposition of another metallic film onthe TiCoN film. Accordingly, the resistances of the metal gates 4 and 5may be reduced by depositing a metal gate film having a lower resistanceon the TiCoN film. In addition, although TiCoN is exemplarily used asthe material for configuring the gate electrodes, the gate electrodesmay be configured from other materials such as TiWN or HfZrN, and may beconfigured from an alloy including two or more metals selected from thegroup consisting of Al, Si, Ti, V, Co, Ni, Ge, Zr, Nb, Mo, Ru, Hf, Taand W, or a nitride of the alloy. Further, although an example whereinoxygen is ion-implanted into the metal gate 5 is exemplified in thepresent embodiment, fluorine may be ion-implanted. For example, forachieving an effect similar to the case where the oxygen ision-implanted under the conditions of an acceleration voltage at 10 kVand a dosage of 1×10¹³ (ions/cm²), fluorine should be ion-implantedunder the conditions of an acceleration voltage at 7 kV and a dosage at8×10¹² (ions/cm²).

As described before, in the present embodiment, the two kinds of metalgate materials for the N-type MISFET metal and P-type MISFET metal areobtained by the content control of a metal nitride film (TiCoN film 4 a)and ion-implantation of oxygen. This leads to formation of metal gateshaving work functions respectively suited to the N-type MISFET andP-type MISFET. As a result, the thresholds of the N-type MISFET and theP-type MISFET can be reduced without involving depletion of the gateelectrodes. In addition, the work functions can be controlled byadjusting the content of the TiCoN film 4 a. Accordingly, even if thework function required of the metal for the N-type MISFET is changed,this can be achieved by controlling the content of the TiCoN film. Thus,a major change of the process conditions in the fabrication is notneeded, whereby productivity is not reduced.

Further, in the method for fabricating the semiconductor deviceaccording to the present embodiment, since there is no step of removinga once-deposited metallic film, the gate insulation film is not damaged.Further, since two kinds of metal gate materials are differentiated fromone another by the ion-implantation, the metal gates can be manufacturedmore easily, at a lower cost and a higher product yield, compared to thecase where the two kinds of metal gate materials are deposited inseparate processes. Further, the gate insulation film has a higherreliability because there are no damages on the gate insulation filmcaused by etching and there is no step of ion-implantation of nitrogen.

Next, a second embodiment of the present invention will be described.FIGS. 8( a) to 8(d) and 9(a) to 9(c) consecutively show a method formanufacturing a semiconductor device according to the presentembodiment. The present second embodiment differs from the firstembodiment in that dummy gate electrodes are formed in advance, andremoved after the activation of impurities implanted in the source anddrain, and then metal gates are formed. By using this method, the gateelectrodes are formed from a TiZrN film or TiHfN film having a lowerresistance against heat in the interface with the gate insulation film.In addition, a low-melting-point metal such as Al may be used forreducing the resistance of the gate electrode.

First, as shown in FIG. 8( a), element isolation regions 2 areselectively formed in the surface area of the silicon substrate 1,similarly to the first embodiment. Subsequently, a silicon oxide filmhaving a thickness of around 2 to 6 nm, for example, is formed as adummy insulation film 13, which is to be removed in a later step.Thereafter, a polysilicon film 26 having a thickness of about 150 nm,for example, and a silicon nitride film 27 having a thickness of about50 nm, for example are formed, to obtain layered films including thepolysilicon film 26 and silicon nitride film 27. The layered films arethen patterned to configure electrode patterns, to thereby obtain dummygate electrodes 28, which are to be removed in a later step.

Subsequently, the extension regions 6, which constitute source and drainimpurity-diffused regions, are formed by an ion-implantation techniqueusing the dummy gate electrodes 28 as a mask. Then, a heat treatment foractivation of impurities is performed under the conditions similar tothose of the first embodiment. Thereafter, a silicon nitride film isdeposited using a CVD technique, and selectively removed using an RIEtechnique, to thereby form side-walls 7 made from a silicon nitride filmand having a width of 20 to 40 nm on the sides of the dummy gateelectrode 28. Then, by an ion-implantation technique using the dummygate electrodes 28 and side walls 7 as a mask, diffused regions 8 whichconstitute source and drain heavily-doped/impurity-diffused regions areformed. Then, a heat treatment is performed for activation of impuritiesunder the conditions similar to those of the first embodiment.Subsequently, a silicide film (not shown) having a thickness of about 40nm, for example, is formed only in the source and drain regions by asalicide process technique using the dummy gate electrodes 28 andside-walls 7 as a mask. Thereafter, an interlayer dielectric film 9 isformed by depositing a silicon oxide film, for example, while using aCVD technique.

Subsequently, as shown in FIG. 8( b), the surface of the interlayerdielectric film 9 is subjected to a planar process using a CMP techniqueto expose therefrom the surface of the dummy gate electrodes 28, i.e.,the surface of the silicon nitride film 27.

Subsequently, as shown in FIG. 8( c), the silicon oxide film 27 on topof the dummy gate electrodes 28 is removed selectively from theinterlayer dielectric film 9 by using phosphoric acid, for example. Thisresults in exposure of the polysilicon film 26. Subsequently, thepolysilicon film 26 is removed selectively from the interlayerdielectric film 9 and side-walls 7 by an etching technique usingradicals of fluorine etc. Then, a wet etching using dilute hydrofluoricacid etc. is performed to remove the dummy insulation film 13 made fromthe silicon oxide film, thereby forming trenches 29. Subsequently, asshown in FIG. 8( d), a high-dielectric-constant insulation film such asalumina film 33 a, for example, which constitutes a gate insulation film33 (refer to FIG. 9( c)), is formed over the entire surface by using anALCVD technique.

Subsequently, as shown in FIG. 9( a), a TiHfN film 30 a having a workfunction of 4.0 to 4.5 eV and suited to the gate electrode material forthe N-type MISFET is deposited by a CVD technique or sputteringtechnique on the alumina film 33 a to a thickness of about 20 nm, forexample.

Subsequently, as shown in FIG. 9( b), regions other than the P-typeMISFET forming regions are covered with a resist 31, followed byion-implantation of fluorine at an acceleration voltage of 10 keV and adosage of around 1×10¹³ ions/cm². This allows the work function of theportion 30 b of the TiHfN film 30 a corresponding to the P-type MISFETforming region 12 to increase by about 0.4 eV compared to the otherportion of the TiHfN film 30 a.

Subsequently, as shown in FIG. 9( c), the resist 31 is removed, followedby a planar process using CMP, to remove the TiHfN film 30 a and thealumina film 33 a on the interlayer dielectric film 9.

Thereby, the interlayer dielectric film 9 is exposed, and the gateinsulation film 33 made of alumina film 33 a and the gate electrode 32 amade of TiHfN film are formed within the trench 29 in the N-type MISFETforming region 11, whereas the gate insulation film made of alumina film33 a and the gate electrode 32 b made of TiHfN film are formed withinthe trench 29 in the P-type MISFET forming region 12.

In the present embodiment, by selectively ion-implanting fluorine intothe TiHfN film 30 a, which constitutes the gate electrode material, thegate electrode 32 a of the N-type MISFET and the gate electrode 32 b ofthe P-type MISFET can be differentiated in the fabrication, and both theN-type MISFET and the P-type MISFET can be operated at lower thresholds.In the present embodiment, the dummy insulation film 13 and dummy gateelectrodes 28 are formed and used as a mask for impurity implantation,followed by performing a heat treatment for activation of theimpurities, removal of the dummy gate electrode 28 and dummy insulationfilm 13, and formation of the gate insulation film 33 and gateelectrodes 32 a and 32 b. This prevents the gate insulation film 33 andgate electrodes 32 a and 32 b from being exposed to the heat treatment.As a result, the TiHfN film having a lower resistance against heat inthe interface with the gate insulation film can be used as a gateelectrode material. It is to be noted that the gate electrode may beformed from a TiZrN film in the present embodiment.

Next, change of the work function will be described in the case wherefilms each made of a metal, alloy or nitride thereof (hereinafterreferred to as collectively metallic film) are layered. The presentinventors found that, when two kinds of metallic films were layered oneon another, the work function of the layered films exhibited a tendencysimilar to that of the case where the materials configuring thesemetallic films were alloyed. More specifically we found that thebehavior of change of the work function when the thickness ratio of thelayered films was changed exhibited a tendency similar to the tendencyof the work function when the content ratio of the alloy was changed.Accordingly, if the relationship between the content ratio and the workfunction of the alloy shown in the first embodiment is known, bylayering the materials configuring the alloy film one on another to formlayered films, the work function of the layered films can be predicted.

FIG. 10( a) is a side view showing the experimental method forinvestigating the relationship between the work function and thethickness ratio of the layered films, and FIG. 10( b) is a graph showingthe influence caused by the average thickness of the TiN film on thework function of the layered films, wherein the average thickness of aTiN film shown in FIG. 10( a) is plotted on abscissa and the workfunction of the layered films shown in FIG. 10( a) is plotted onordinate. As shown in FIG. 10( a), a 10-nm-thick Si thermal oxide film(SiO₂) 22 is formed on a P-type Si substrate (P—Si) 21, followed byconsecutively forming thereon a TiN film 23 and a Co film 24 by asputtering technique. It is to be noted that the TiN film 23 may beomitted. In this step, the thickness of the intermediate TiN film 23 ischanged within the range from 0 nm (the case where no TiN film isformed) to 1.0 nm. The thickness of the CoN film 24 is set at 30 nm. TheSi thermal oxide film 22, TiN film 23 and CoN film 24 are patterned toconfigure a circle having a diameter of around 0.1 mm. Then, the workfunction of the layered films 25 including the TiN film 23 and CoN film24 is measured.

As shown in FIG. 10( b), the work function increases with the increaseof the thickness of the TiN film 23 within the thickness range of theTiN film 23 between 0 and 0.5 nm, whereas the work function decreaseswith the increase of the thickness of the TiN film 23 within thethickness range of the TiN film 23 from 0.5 to 1.0 nm. This is similarto the change of the work function when TiN is introduced into CoN inFIG. 1 shown before. That is, when the TiN film 23 is provided tounderlie the CoN film 24, an effect similar to the effect of alloying byintroducing TiN in CoN is obtained. Accordingly, by layering the TiNfilm and CoN film one on another, the work function of the whole layeredfilms can be controlled. This is considered due to the fact thatelectron dipoles are formed in the interface between the TiN film andthe CoN film to change the work function. It is to be noted that sincethe TiN film 23 is formed by a sputtering technique, the TiN film isgrown in an island structure having convex and concave surfaces. If theTiN film is formed by an atomic layer growth technique etc., a similareffect can be obtained with a smaller film thickness. Thus, it ispreferable that the TiN film be a continuous film. The average thicknessof the TiN film is a thickness obtained by measuring the concentrationprofile of the TiN film and calculating the thickness thereof based onthe concentration profile while assuming it is a continuous film made ofpure TiN.

By using the above characteristic during differentiation of the metalgate of the N-type MISFET and the metal gate of the P-type MISFET fromone another in the fabrication thereof, the work functions of the metalgates can be controlled as desired and the process damaging the gateinsulation film by removal of the gate electrodes can be avoided,

A third embodiment of the present invention will be described. FIG. 11shows a semiconductor device of the present embodiment. As shown in FIG.11, the semiconductor device of the third embodiment differs from thesemiconductor device of the above first embodiment in that the gateelectrode of the N-type MISFET is comprised of layered films. It is tobe noted that, although the gate electrode of the P-type MISFET is alsolayered in two steps, the composition of the layers is same and thus itis difficult to distinguish the layers from one another after thelayering. The structure of the semiconductor device of the thirdembodiment is similar to the structure of the semiconductor device ofthe first embodiment except for the gate electrodes.

In the present embodiment, a metal gate 14 is formed on the gateinsulation film 3 in the N-type MISFET forming region 11 whereas a metalgate 15 is formed on the gate insulation film 3 in the P-type MISFETforming region 12. The metal gate 14 in the N-type MISFET forming region11 is formed as a three-layer film. A TiCoN film 16 is formed as abottom layer in contact with the gate insulation film 3 in the metalgate 14. The average thickness of the TiCoN film 16 is 0.5 nm, forexample, the atomic ratio thereof is T:Co=5:95, for example, and workfunction thereof is 4.9 eV. A TiN film 17 having an average thickness ofabout 5 nm or above, for example, is formed on the TiCoN film 16.Another TiCoN film 18 having an average thickness of about 200 nm, forexample, is formed on the TiN film 17. The content ratio and workfunction of the TiCoN film 18 are similar to those of the TiCoN film 16.

On the other hand, the metal gate 15 in the P-type MISFET forming region12 is formed as a two-layer film. A TiCoN film 16 having an averagethickness of 0.5 nm, for example, and an atomic ratio of Ti:Co=5:95 isformed as the bottom layer in contact with the gate insulation film 3 inthe metal gate 15. A TiCoN film 19 having an average thickness of about200 nm, for example, and an atomic ratio of Ti:Co=5:95, for example, isformed on the TiCoN film. 16. The work function of the metal gate 14 is4.4 eV, for example, whereas the work function of the metal gate 15 is4.9 eV, for example. The thickness of the TiCoN films 18 and 19 may be 5nm, for example, and a low-resistance metallic film such as made of Aland having a thickness of about 200 nm, for example, may be layered onthe TiCoN films 18 and 19.

It is preferable that the average thickness of the TiCoN film be 0.1 to5 nm. If the average thickness of the TiCoN film 16 is smaller than 0.1nm, it means that an average thickness is smaller than one atomic layerand thus a continuous film cannot be obtained. Thus, the effect forprotecting the gate insulation film against the etching is reduced. Onthe other hand, if the average thickness of the TiCoN film 16 is largerthan 5 nm, the contribution of the TiN film 17 to the work function ofthe whole metal gate 14 is reduced, and thus the work function of thewhole metal gate 14 becomes excessively higher.

Next, a method for manufacturing the semiconductor device of the thirdembodiment will be described. First, by using a process similar to thatfor the first embodiment, element isolation regions 2 are formed in thesurface area of the silicon substrate 1, followed by forming the gateinsulation film 3 on the silicon substrate 1. Subsequently, as shown inFIG. 11, the TiCoN film 16 is formed on the gate insulation film 3 to athickness of 0.5 nm, for example. The TiCoN film 16 has an atomic ratioof Ti:Co=5:95, for example, and this content ratio allows the workfunction of the TiCoN film 16 to assume 4.9 eV, for example, suited tothe gate electrode of the P-type MISFET.

Subsequently, the TiN film 17 is layered on the TiCoN film 16 to athickness of 5 nm or above, followed by removing only a portion of theTiN film 17 on the P-type MISFET forming region 12 by using aphotolithographic technique and an RIE (reactive ion etching) technique.Since the etch selectivity between TiCoN and TiN is large, only the TiNfilm 17 is removed without etching the TiCoN film 16.

Subsequently, another TiCoN film is formed on the TiN film 17 in theN-type MISFET forming region 11 and on the TiCoN film 16 in the P-typeMISFET forming region 12. This allows the TiCoN film 18 to be formed onthe TiN film 17, and allows the TiCoN film 19 to be formed on the TiCoNfilm 16. Then, the TiCoN film 16, TiN film 17, TiCoN film 18 and TiCoNfilm 19 are patterned. As a result, the metal gate 14 including theTiCoN film 16, TiN film 17 and TiCoN film 18 is formed, whereas themetal gate 15 including the TiCoN film 16, TiN film 17, TiCoN film 18and TiCoN film 19 is formed.

Thereafter, the extension regions 6 and diffused regions 8 are formed inthe surface area of the silicon substrate 1 by using a process similarto the first embodiment (refer to FIGS. 7( c) and 7(d)), followed byforming the side-walls 7 and interlayer dielectric film 9 on the gateinsulation film 3, thereby achieving the semiconductor device of thepresent embodiment.

As described above, in the present embodiment, two kinds of metal gatematerials for the N-type MISFET metal and P-type MISFET metal aremanufactured by the content control and control of the layered structureof the metal nitride film. Thereby, the work function of the metal gateis controlled to differentiate the metal gate of the N-type MISFET andthe metal gate of the P-type MISFET in fabrication thereof, withoutdamaging the gate insulation film. As a result, a semiconductor devicehaving lower thresholds for both the N-type MISFET and P-type MISFET canbe obtained, without involving depletion of the gate electrodes. Inaddition, in the present embodiment, since there is no damage of thegate insulation film caused by the etching as well as noion-implantation of nitrogen, the gate insulation film has a higherreliability. Further, since the fabrication is easy to achieve, thefabrication cost is lower and the product yield is higher.

As described in the background technology, for differentiation of theN-type MISFET and P-type MISFET in the conventional technique, forexample, a metallic film for the gate electrode of the N-type MISFET isformed on the entire surface of the wafer, then a portion of themetallic film on the P-type MISFET is removed, and another metallic filmfor the gate electrode of the P-type MISFET is again formed. There isanother technique wherein, after a dummy gate electrode is formed forthe P-type MISFET, a metallic film for the gate electrode of the N-typeMISFET is formed on the entire surface, followed by removing the dummygate electrode and forming another metallic film for the gate electrodeof the P-type MISFET on the gate insulation film of the P-type MISFET.In either fabrication process, there is a step of removing the metallicfilm for the gate electrode or dummy gate electrode, to damage the gateinsulation film in this process.

On the contrary, in the present embodiment, one of the metal gates isformed from layered films to differentiate the N-type MISFET and theP-type MISFET in the fabrication. This process does not remove themetallic film in contact with the gate insulation film in both theN-type MISFET and P-type MISFET, and controls to change the workfunction in both the cases of layering the same metal and the differentmetal. Thus, the gate insulation film is not damaged.

Although the case of layering the TiCoN film and the TiN film is shownin the present embodiment, the present invention is not limited thereto.The above property is obtained not only in the case of TiN and CoN, andthe work function can be controlled in the case of forming a layeredstructure including metals such as Al, Si, Ti, V, Cr, Fe, Co, Ni, Cu,Zn, Ge, Zr, Nb, Mo, Ru, Rh, Pd, Hf, Ta, W, Re, Os, Ir and Pt, alloysincluding these metallic materials and nitrides of these metals oralloys. It is to be noted that different work functions can be obtainedfrom the metallic materials selected. In the combination of thesemetallic materials, by selecting a combination which allows a higheretch selectivity and first forming a metallic film having a lower etchrate, the metal gate can be obtained without damaging the gateinsulation film. Oxygen or fluorine may be added in the TiCoN film andTiN film in the present embodiment, similarly to the first embodiment,whereby work function of each film can be controlled in a wider range.

If there is a high-temperature process at a temperature equal to orabove 400 degrees C. after formation of the gate electrodes, and a puremetal is used as a film underlying the metal gates, then there will be areaction in the interface between the pure metal film and the gateinsulation film (for example, silicon oxide film) in thehigh-temperature process, thereby deviating the threshold from thedesign value. Thus, it is preferable to select a metal nitride filmhaving a higher thermal stability as the film underlying the metal gate.However, it is possible to form dummy gate insulation film and dummygate electrode, followed by ion-implantation and activation ofimpurities, removal of the dummy gate insulation film and dummy gateelectrode and formation of the gate insulation film and gate electrodein the present embodiment, as in the second embodiment. This allows amaterial having a relatively lower resistance against heat can be usedas the gate electrode material. For example, a HfN film is used as thegate electrode of the N-type MISFET, and layered films including a HfNfilm and a WN film may be sued as the gate electrode of the P-typeMISFET.

According to the embodiments of the present invention as detailedheretofore, formation of the gate electrode of themetal-insulator-semiconductor field-effect transistor by using amaterial wherein a metal, an alloy or a metal nitride is doped withoxygen or fluorine allows the work function of the gate electrode to becontrolled as desired, thereby achieving a semiconductor deviceincluding metal-insulator-semiconductor field-effect transistors havinglower thresholds. In addition, formation of a film made of a metal,alloy or metal nitride in the N-type MISFET forming region and theP-type MISFET forming region and ion-implantation of oxygen or fluorineinto the film allows the metal gates of the N-type MISFET and P-typeMISFET to be differentiated in fabrication, thereby operating theMISFETs at respective lower threshold voltages. In addition, the twokinds of metal gates can be manufactured at a lower cost and a higherproduct yield. Further, since there is no damage on the gate insulationfilm, the reliability of the gate insulation film is not degraded. Inthese gate electrodes, since there occurs no depletion, it is suited toa higher speed operation of the semiconductor device having a gatelength of 0.1 μm or less.

Although the present invention is described with reference to thepreferred embodiments thereof, the present invention is not limited onlyto the structures of the embodiments, and various modifications oralterations can be 20 made the above embodiments without departing fromthe scope of the present invention.

1. A semiconductor device comprising an N-channelmetal-insulator-semiconductor field-effect transistor and a P-channelmetal-insulator-semiconductor field-effect transistor, characterized inthat said N-channel metal-insulator-semiconductor field-effecttransistor includes a gate electrode made of a metal, alloy or metalnitride film doped with oxygen or fluorine, and that said P-channelmetal-insulator-semiconductor field-effect transistor includes a gateelectrode formed in a common layer with said gate electrode of saidN-channel metal-insulator-semiconductor field-effect transistor and madefrom a portion of said common layer doped with oxygen or fluorine moreheavily than said gate electrode of said N-channelmetal-insulator-semiconductor field-effect transistor.
 2. Asemiconductor device comprising an N-channelmetal-insulator-semiconductor field-effect transistor and a P-channelmetal-insulator-semiconductor field-effect transistor, characterized inthat said N-channel metal-insulator-semiconductor field-effecttransistor includes a gate electrode made from a metal, alloy or metalnitride film, and that said P-channel metal-insulator-semiconductorfield-effect transistor includes a gate electrode formed in a commonlayer with said gate electrode of said N-channelmetal-insulator-semiconductor field-effect transistor and made from aportion of said common layer doped with oxygen or fluorine.
 3. Thesemiconductor device according to any one of claims 1 or 2, wherein amaterial configuring said gate electrode of said N-channelmetal-insulator-semiconductor field-effect transistor and said gateelectrode of said P-channel metal-insulator-semiconductor field-effecttransistor is polycrystalline or amorphous and has an average grain sizeof 50 nm or less.
 4. The semiconductor device according to any one ofclaims 1 or 2, wherein a material configuring said gate electrode ofsaid N-channel metal-insulator-semiconductor field-effect transistor andsaid gate electrode of said P-channel metal-insulator-semiconductorfield-effect transistor is made of an alloy including two or more metalsselected from the group consisting of Al, Si, Ti, V, Co, Ni, Ge, Zr, Nb,Mo, Ru, Hf, Ta and W or a nitride of said alloy.
 5. The semiconductordevice according to claim 4, wherein said material configuring said gateelectrode is made of said nitride of said alloy including Ti and a metalselected from the group consisting of Al, Si, V, Co, Ni, Ge, Zr, Nb, Mo,Ru, Hf, Ta and W.
 6. The semiconductor device according to 5, whereinsaid material configuring said gate electrode is made of TiCoN or TiWN.7. The semiconductor device according to claim 5, wherein said materialconfiguring said gate electrode of said N-channelmetal-insulator-semiconductor field-effect transistor and said gateelectrode of said P-channel metal-insulator-semiconductor field-effecttransistor is a nitride of an alloy including two or more metalsselected from the group consisting of Al, Hf and Zr.
 8. Thesemiconductor device according to claim 7, wherein a materialconfiguring said gate electrode of said N-channelmetal-insulator-semiconductor field-effect transistor and said gateelectrode of said P-channel metal-insulator-semiconductor field-effecttransistor is HfZrN.
 9. The semiconductor device according to any one ofclaims 1 or 2, wherein an oxygen or fluorine profile of said gateelectrode of said P-channel metal-insulator-semiconductor field-effecttransistor with respect to a thickness direction thereof has a peakwithin 5 nm from an interface with said gate insulation film.
 10. Thesemiconductor device according to any one of claims 1 or 2, wherein awork function of a material configuring said gate electrode of saidP-channel metal-insulator-semiconductor field-effect transistor is 0.1eV higher than a work function of a material configuring said gateelectrode of said N-channel metal-insulator-semiconductor field-effecttransistor.
 11. The semiconductor device according to claim 3, wherein amaterial configuring said gate electrode of said N-channelmetal-insulator-semiconductor field-effect transistor and said gateelectrode of said P-channel metal-insulator-semiconductor field-effecttransistor is made of an alloy including two or more metals selectedfrom the group consisting of Al, Si, Ti, V, Co, Ni, Ge, Zr, Nb, Mo, Ru,Elf, Ta and W or a nitride of said alloy.
 12. The semiconductor deviceaccording to claim 5, wherein an oxygen or fluorine profile of said gateelectrode of said P-channel metal-insulator-semiconductor field-effecttransistor with respect to a thickness direction thereof has a peakwithin 5 nm from an interface with said gate insulation film.
 13. Thesemiconductor device according to claim 6, wherein an oxygen or fluorineprofile of said gate electrode of said P-channelmetal-insulator-semiconductor field-effect transistor with respect to athickness direction thereof has a peak within 5 nm from an interfacewith said gate insulation film.
 14. The semiconductor device accordingto claim 7, wherein an oxygen or fluorine profile of said gate electrodeof said P-channel metal-insulator-semiconductor field-effect transistorwith respect to a thickness direction thereof has a peak within 5 nmfrom an interface with said gate insulation film.
 15. The semiconductordevice according to claim 8, wherein an oxygen or fluorine profile ofsaid gate electrode of said P-channel metal-insulator-semiconductorfield-effect transistor with respect to a thickness direction thereofhas a peak within 5 nm from an interface with said gate insulation film.16. The semiconductor device according to claim 5, wherein a workfunction of a material configuring said gate electrode of said P-channelmetal-insulator-semiconductor field-effect transistor is 0.1 eV higherthan a work function of a material configuring said gate electrode ofsaid N-channel metal-insulator-semiconductor field-effect transistor.17. The semiconductor device according to claim 6, wherein a workfunction of a material configuring said gate electrode of said P-channelmetal-insulator-semiconductor field-effect transistor is 0.1 eV higherthan a work function of a material configuring said gate electrode ofsaid N-channel metal-insulator-semiconductor field-effect transistor.18. The semiconductor device according to claim 7, wherein a workfunction of a material configuring said gate electrode of said P-channelmetal-insulator-semiconductor field-effect transistor is 0.1 eV higherthan a work function of a material configuring said gate electrode ofsaid N-channel metal-insulator-semiconductor field-effect transistor.19. The semiconductor device according to claim 8, wherein a workfunction of a material configuring said gate electrode of said P-channelmetal-insulator-semiconductor field-effect transistor is 0.1 eV higherthan a work function of a material configuring said gate electrode ofsaid N-channel metal-insulator-semiconductor field-effect transistor.